Interface studies of N2 plasma-treated ZnSnO nanowire transistors using low-frequency noise measurements.

نویسندگان

  • Seongmin Kim
  • Hwansoo Kim
  • David B Janes
  • Sanghyun Ju
چکیده

Due to the large surface-to-volume ratio of nanowires, the quality of nanowire-insulator interfaces as well as the nanowire surface characteristics significantly influence the electrical characteristics of nanowire transistors (NWTs). To improve the electrical characteristics by doping or post-processing, it is important to evaluate the interface characteristics and stability of NWTs. In this study, we have synthesized ZnSnO (ZTO) nanowires using the chemical vapor deposition method, characterized the composition of ZTO nanowires using x-ray photoelectron spectroscopy, and fabricated ZTO NWTs. We have characterized the current-voltage characteristics and low-frequency noise of ZTO NWTs in order to investigate the effects of interface states on subthreshold slope (SS) and the noise before and after N2 plasma treatments. The as-fabricated device exhibited a SS of 0.29 V/dec and Hooge parameter of ~1.20 × 10(-2). Upon N2 plasma treatment with N2 gas flow rate of 40 sccm (20 sccm), the SS improved to 0.12 V/dec (0.21 V/dec) and the Hooge parameter decreased to ~4.99 × 10(-3) (8.14 × 10(-3)). The interface trap densities inferred from both SS and low-frequency noise decrease upon plasma treatment, with the highest flow rate yielding the smallest trap density. These results demonstrate that the N2 plasma treatment decreases the interface trap states and defects on ZTO nanowires, thereby enabling the fabrication of high-quality nanowire interfaces.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Role of self-assembled monolayer passivation in electrical transport properties and flicker noise of nanowire transistors.

Semiconductor nanowires have achieved great attention for integration in next-generation electronics. However, for nanowires with diameters comparable to the Debye length, which would generally be required for one-dimensional operation, surface states degrade the device performance and increase the low-frequency noise. In this study, single In(2)O(3) nanowire transistors were fabricated and cha...

متن کامل

Analysis of Low Frequency Drain Current Model for Silicon Nanowire Gate-All-Around Field Effect Transistor

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effe...

متن کامل

Optimization and Characterization Of Gate Electrode Dependent Flicker Noise in Silicon Nanowire Transistors

The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, Ion / Ioff and ...

متن کامل

Optimal signal-to-noise ratio for silicon nanowire biochemical sensors.

The signal-to-noise ratio (SNR) for silicon nanowire field-effect transistors operated in an electrolyte environment is an essential figure-of-merit to characterize and compare the detection limit of such devices when used in an exposed channel configuration as biochemical sensors. We employ low frequency noise measurements to determine the regime for optimal SNR. We find that SNR is not signif...

متن کامل

1/f noise measurements on indium antimonide metal–oxide–semiconductor field-effect transistors

We performed the 1/f noise measurements on n-channel indium antimonide ~InSb! metal–oxide– semiconductor field-effect transistors ~MOSFETs! biased in linear and saturation regions operated at 77 K. Through the investigation of the dependence of drain voltage noise power spectral density on gate and drain bias, we have estimated the oxide–semiconductor interface trap density as a function of ene...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • Nanotechnology

دوره 24 30  شماره 

صفحات  -

تاریخ انتشار 2013